1. Field of the Invention
The invention relates to a semiconductor device, in particular, a semiconductor device having a structure that enhances the breakdown voltage.
2. Description of the Related Art
A semiconductor device includes an LDMOS transistor. The DMOS is the abbreviation of a Double-Diffused Metal Oxide Semiconductor. A DMOS transistor in which an electric current flows in the lateral direction is the LDMOS transistor. The LD is the abbreviation of Laterally Diffused. The LDMOS transistor is widely used for a power supply circuit, a driver circuit and so on.
In a MOS transistor in which the source and drain layers containing a high concentration of impurities are formed near the gate channel layer, when a reverse bias is applied to the drain layer, a depletion layer extends from the drain layer into the semiconductor layer thereunder corresponding to the impurity concentration of the semiconductor layer. However, the depletion layer does not extend in the lateral direction from the drain layer near the gate channel layer into the semiconductor layer as the gate channel layer due to the effect of the electric field of the gate electrode and the drain layer. Therefore, since the electric field strength in the lateral direction of the drain layer is much larger than in the downward direction of the drain layer to cause dielectric breakdown, it is difficult to realize a high breakdown voltage MOS transistor.
This problem may be solved by increasing the thickness of the gate insulation film to weaken the electric field from the gate electrode. However, since the thickness of the gate insulation film is decreased according as the progress of the process technology, a so-called offset drain structure is used as a solution.
This is a structure in which a high concentration drain layer is disposed away from a gate channel layer. In this structure, a so-called drift layer of which the impurities is of the same type as that of the drain layer and the concentration is lower than that of the drain layer is formed between the gate channel layer and the high concentration drain layer, so that the depletion layer extends more easily from the high concentration drain layer in the lateral direction to decrease the electric field strength in the lateral direction and enhance the breakdown voltage.
The drift layer mentioned above fauns a path for an electric current between the source layer and the drain layer when the gate channel layer is inverted and the DMOS transistor turns on, and it is thus preferable for the drift layer to have as low resistance as possible. In other words, it is advantageous that the impurity concentration of the drift layer is higher since the on-resistance becomes lower. A tradeoff relation thus occurs between this and the effect described above that the impurity concentration of the drift layer is decreased to widen the depletion layer extending toward the drift layer in order to minimize the decrease of the breakdown voltage in the front surface and obtain a desired breakdown voltage.
Therefore, the impurity concentration of the drift layer need be determined without excess and deficiency in order to realize both the low on-resistance and high breakdown voltage appropriately, and some other factor may cause the decrease of the breakdown voltage. The inventors found that the decrease of the breakdown voltage occurs in a gate width end portion as described below even when the impurity concentration of the drift layer is determined appropriately from both the aspects of on-resistance and breakdown voltage. It is necessary to prevent the decrease of the breakdown voltage in the gate width end portion.